The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Apr. 10, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marco Sforzin, Cernusco Sul Naviglio, IT;

Christophe Vincent Antoine Laurent, Agrate Brianza, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/15 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/152 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); H03M 13/1575 (2013.01);
Abstract

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.


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Sforzin, Marco. (2026). Fast multi-payload-length error-correcting system and methods (U.S. Patent No. 12542567). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12542567

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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