The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Aug. 03, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Xiang Yang, Santa Clara, CA (US);

Eric Fu, Sunnyvale, CA (US);

Albert Chen, Milpitas, CA (US);

Jonathan Huynh, San Jose, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/12 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/12 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01);
Abstract

A memory device includes a set of memory cells and a control circuit coupled to the set of memory cells. The control circuit is configured to transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level. While the wordline voltage settles at the second wordline voltage level, the control circuit cuts off current to the target memory cell by at least one of temporarily ramping down a bitline voltage from a first bitline voltage level to a second bitline voltage level, temporarily ramping down a select gate voltage from a first select gate voltage level to a second select gate voltage level, and temporarily ramping up a source line voltage from a first source level to a second source level.


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