The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Mar. 18, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hidehiro Fujiwara, Hsinchu, TW;

Haruki Mori, Hsinchu, TW;

Wei-Chang Zhao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01); G06F 7/544 (2006.01); G11C 7/10 (2006.01); G11C 11/412 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G06F 7/5443 (2013.01); G11C 7/1006 (2013.01); G11C 11/412 (2013.01); G11C 11/54 (2013.01); G06F 2207/4824 (2013.01);
Abstract

A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.


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