The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Nov. 20, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yi-Ching Chen, Kaohsiung, TW;

Ching-Ling Lin, Kaohsiung, TW;

Wen-An Liang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/321 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/32115 (2013.01); H01L 21/3065 (2013.01); H01L 21/31055 (2013.01); H01L 21/32055 (2013.01); H01L 21/3212 (2013.01); H01L 21/32135 (2013.01); H01L 21/32136 (2013.01); H01L 21/32137 (2013.01); H10D 30/024 (2025.01);
Abstract

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.


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