The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Oct. 27, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Soo Doo Chae, Albany, NY (US);

Matthew Baron, Albany, NY (US);

Hojin Kim, Albany, NY (US);

Sunghil Lee, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/30625 (2013.01); H01L 21/76224 (2013.01); H10D 84/0151 (2025.01);
Abstract

A method for fabricating semiconductor devices is disclosed. The method includes forming, on a first side of a substrate, a first stack and a second stack. The method includes etching, from the first side, a portion of the substrate interposed between the first and second stacks to form a recess. The method includes filling the recess with a dielectric material to form an isolation structure. The method includes forming, on the first side, one or more first interconnect structures over the first and second stacks. The method includes removing, from a second side of the substrate opposite to the first side, a remaining portion of the substrate. The method includes forming a via structure extending through at least the isolation structure. The method includes forming, on the second side, one or more second interconnect structures.


Find Patent Forward Citations

Chae, Soo. (2026). Methods for fabricating isolation structures using directional beam process (U.S. Patent No. 12538560). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12538560

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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