The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jul. 10, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Masanori Tsutsumi, Yokkaichi, JP;

Keita Akasaki, Yokkaichi, JP;

Tomohiro Kubo, Yokkaichi, JP;

Shinsuke Yada, Yokkaichi, JP;

Takaaki Iwai, Nagoya, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.


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