The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Jan. 10, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Cheng-Yi Lin, Hsinchu, TW;
Tsung-Yang Hung, Zhubei, TW;
Ankita Patidar, San Jose, CA (US);
Ming-Yih Wang, Hsinchu, TW;
Sandeep Kumar Goel, Dublin, CA (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.