The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Dec. 14, 2022
Ansys, Inc., Canonsburg, PA (US);
Lang Lin, Cupertino, CA (US);
Kayhan Kucukcakar, Los Altos, CA (US);
Jimin Wen, Pleasanton, CA (US);
Norman Chang, Fremont, CA (US);
Preeti Gupta, San Jose, CA (US);
Hua Chen, Chengdu, CN;
ANSYS, INC., Canonsburg, PA (US);
Abstract
Techniques for security vulnerability assessment of security-sensitive circuit designs are described. A placement of security-sensitive components of a design may be based on constraints related to how far apart a relevant set of security-sensitive components are allowed without consuming too much power and how to optimize the placement to minimize electromagnetic side-channel leakage or other security vulnerabilities. In one embodiment, a method may receive data that includes a representation of a design of an IC and may identify security-sensitive components of the design from the data. The method may determine a placement for the design based on constraints on a level of security vulnerabilities of the security-sensitive components and may perform a power simulation for the design based on the placement. The method may generate an assessment of the level of security vulnerabilities of the security-sensitive components based on the power simulation to adjust the placement for the design.