The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Jun. 02, 2022
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Yung-Yu Chen, Hsinchu, TW;
Wen-Li Cheng, Hsinchu, TW;
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/00 (2006.01); G06F 30/30 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G03F 7/705 (2013.01); G06F 30/392 (2020.01);
Abstract
A layout is used in a computational lithography process. For example, the layout may be the layout of the lithographic mask or the layout of the desired resist shape. The layout is made up of multiple disjoint shapes. At least some of the disjoint shapes are represented by parametric curve representations, rather than polygons or other rectilinear representations. The parametric curve representations of the shapes are then used in the computational lithography process.
Chen, Yung-Yu. (2026). Representing lithographic layouts using parametric curves (U.S. Patent No. 12535741). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12535741
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile