The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Dec. 09, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kulachet Tanpairoj, San Mateo, CA (US);

Nadav Grosz, Broomfield, CO (US);

James Fitzpatrick, Laguna Niguel, CA (US);

Jianmin Huang, San Carlos, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0897 (2016.01); G06F 12/02 (2006.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 2212/1024 (2013.01);
Abstract

Methods, systems, and devices for a multi-tier cache for a memory system are described. A memory device may include memory cells configured as cache storage and memory cells configured as main storage. The cache storage may be a multi-tier cache and may include sets of different types of memory cells or memory cells operated as different types of memory cells, with different latencies, storage densities, or other performance characteristics. The memory device or a controller or host system for the memory device may determine the set of memory cells within the multi-tier cache to which a set of data is to be written, or may move the set of data within the multi-tier cache or between the multi-tier cache and the main storage, based on one or more of a variety of performance considerations.


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