The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Jun. 03, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Yu-Ming Chen, Taipei, TW;
Szu-Ying Chen, Hsinchu, TW;
Yen-Chun Huang, New Taipei, TW;
Sen-Hong Syue, Zhubei, TW;
Huicheng Chang, Tainan, TW;
Yee-Chia Yeo, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.