The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jan. 19, 2024
Applicant:

Ememory Technology Inc., Hsin-chu, TW;

Inventors:

Chia-Jung Hsu, Hsinchu County, TW;

Yun-Jen Ting, Hsinchu County, TW;

Cheng-Heng Chung, Hsinchu County, TW;

Chun-Hsiao Li, Hsinchu County, TW;

Tsung-Mu Lai, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 20/25 (2023.02); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H10B 41/35 (2023.02); H10B 43/35 (2023.02);
Abstract

A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.


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