Multi-chip module (mcm) with scalable high bandwidth memory

Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes an active silicon substrate and a memory interface circuit configured to support N memory channels. The memory interface circuit has a primary interface for coupling to a host memory interface via the N memory channels. A first HBM stack of memory die is disposed on the active silicon substrate and coupled to a secondary interface of the memory interface circuit. The first HBM stack dedicated to a first subset of the N data channels and a first data transfer rate. A second HBM stack of memory die is disposed on the active silicon substrate. The second HBM stack is positioned inline with the first HBM stack and the memory interface circuit and coupled to the secondary interface of the memory interface circuit. The second HBM stack is dedicated to a second subset of the N data channels and exhibits a second data transfer rate. The first HBM stack and the second HBM stack are configured to collectively support the N channels and exhibit an aggregate data rate that is a sum of the first data rate and the second data rate.