The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Sep. 06, 2022
Micron Technology, Inc., Boise, ID (US);
Jun Rong Tan, Singapore, SG;
Keen Wah Chow, Singapore, SG;
Hao Ting Teo, Singapore, SG;
Hoong Shing Wong, Singapore, SG;
Micron Technology, Inc., Boise, ID (US);
Abstract
Methods, systems, and devices for techniques to manufacture inter-layer vias are described. In some examples, a manufacturing process for a via to one or more metal lines within an integrated circuit may not include forming a metal pad for the via. For example, the manufacturing process may include forming a layer of dielectric material over a set of metal lines. The manufacturing process may further include forming a cavity through the dielectric layer (e.g., using an etching procedure), exposing the upper surfaces and sidewalls of one or more metal lines of the set. Subsequently, the via may be formed by depositing a conductive material within the cavity. In some cases, the conductive material may be deposited to contact the sidewalls of the one or more metal lines. Such an assembly may establish electrical connection to other electrical components of the integrated circuit.