The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jul. 29, 2024
Applicant:

Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);

Inventors:

Belgacem Haba, Saratoga, CA (US);

Ron Zhang, Sunnyvale, CA (US);

Kyong-Mo Bang, Fremont, CA (US);

Suhail Jaan Sadiq, Dublin, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/46 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/46 (2013.01); H01L 23/5384 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08225 (2013.01); H01L 2225/06572 (2013.01);
Abstract

A device package comprising an integrated cooling assembly comprising a semiconductor stack and a cooling channel, wherein the semiconductor stack comprises a first semiconductor device and a second semiconductor device stacked vertically above the first semiconductor device; and spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device away from the second semiconductor device, the spacers and the opposing surfaces of the first and second semiconductor devices collectively define the cooling channel therebetween; and the spacers comprise via electrically connecting the first semiconductor device and the second semiconductor device.


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