Memory devices with reduced bit line capacitance and methods of manufacturing thereof

Abstract

A semiconductor device includes a first memory cell in a 4CPP architecture; a second memory cell formed in the 4CPP architecture and physically disposed next to the first memory cell along a first lateral direction; a first word line extending along the first lateral direction and operatively coupled to the first memory cell; a second word line extending along the first lateral direction and operatively coupled to the first memory cell; a third word line extending along the first lateral direction and operatively coupled to the second memory cell; a fourth word line extending along the first lateral direction and operatively coupled to the second memory cell; a first bit line extending along a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first memory cell; and a second bit line extending along the second lateral direction and operatively coupled to the second memory cell.