The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
May. 09, 2024
Nxp Usa, Inc., Austin, TX (US);
Ke Zhang, Dripping Springs, TX (US);
Henning Fritz Spruth, Austin, TX (US);
Qadeer Qureshi, Dripping Springs, TX (US);
Christopher Michael Falk, Dripping Springs, TX (US);
Rajesh Padinzhara Rajan, Austin, TX (US);
NXP USA, Inc., Austin, TX (US);
Abstract
A method for physical-aware power profile optimization during memory test includes creating a plurality of scheduling buckets, wherein each scheduling bucket includes one or more sequentially executed test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence including a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to a test time budget. A power profile is optimized by determining a respective optimized start time of at least one test sequence from at least a physical distance between two groups of memories controlled by respective BIST controllers. The respective optimized start time is assigned to the at least one test sequence.