The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2026
Filed:
Jan. 31, 2023
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Yi-Ting Chen, New Taipei, TW;
Sung-Hsin Yang, Tainan, TW;
Chen-Chieh Chiang, Kaohsiung, TW;
Jung-Chi Jeng, Tainan, TW;
Ling-Sung Wang, Tainan, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.