The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Dec. 30, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Julien Frougier, Albany, NY (US);

Heng Wu, Guilderland, NY (US);

Nicolas Loubet, Guilderland, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/0193 (2025.01);
Abstract

An exemplary semiconductor apparatus includes a substrate that includes a first semiconductor. The substrate includes a main body and first and second island portions protruding upward from the main body. The apparatus also includes a bottom dielectric isolation layer that covers the substrate; a PFET with a plurality of gate-all-around (GAA) vertical channel fins above the first island portion and the bottom dielectric isolation layer; and an NFET with a plurality of gate-all-around (GAA) horizontal nanosheet layers above the second island portion and the bottom dielectric isolation layer.


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