The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Feb. 12, 2024
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Michael A. Stuber, Carlsbad, CA (US);

Christopher N. Brindle, Poway, CA (US);

Dylan J. Kelly, San Diego, CA (US);

Clint L. Kemerling, Escondido, CA (US);

George P. Imthurn, San Diego, CA (US);

Robert B. Welstand, San Diego, CA (US);

Mark L. Burgener, San Diego, CA (US);

Alexander Dribinsky, Naperville, IL (US);

Tae-Youn Kim, Irvine, CA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H03K 17/16 (2006.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6711 (2025.01); H03K 17/162 (2013.01); H10D 30/6739 (2025.01); H10D 30/6743 (2025.01); H10D 30/6744 (2025.01); H10D 30/6759 (2025.01); H10D 86/201 (2025.01);
Abstract

A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge. Determinations are made of effects of an uncontrolled accumulated charge and a controlled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the determinations, and the circuit is operated using techniques for ACC operatively coupled to the SOI MOSFET. In one embodiment, the ACC techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.


Find Patent Forward Citations

Stuber, Michael. (2026). Method and apparatus improving gate oxide reliability by controlling accumulated charge (U.S. Patent No. 12520525). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12520525

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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