The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Jan. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ling Mei Lin, Tainan, TW;

Yu-Chang Jong, Hsinchu, TW;

Chih-Hsiung Huang, Hsinchu County, TW;

Yu-Hsien Chu, Kaohsiung, TW;

Wen-Chih Chiang, Hsinchu, TW;

Chih-Ming Lee, Tainan, TW;

Cheng-Ming Wu, Tainan, TW;

Pei-Lun Wang, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/64 (2025.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/64 (2025.01); H01L 21/0206 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02255 (2013.01); H01L 21/02263 (2013.01); H01L 21/02304 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H10D 30/028 (2025.01); H10D 62/103 (2025.01); H10D 62/152 (2025.01); H10D 64/01 (2025.01); H10D 64/514 (2025.01);
Abstract

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.


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