The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Apr. 08, 2024
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Sergey Yuferev, Villach, AT;

Josef Hoeglauer, Heimstetten, DE;

Gerhard Noebauer, Villach, AT;

Hao Zhuang, Hohenbrunn, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/49537 (2013.01); H01L 23/49575 (2013.01); H01L 25/071 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01);
Abstract

A method for manufacturing a semiconductor package includes: providing a leadframe having component positions each of which includes a die pad; providing semiconductor dies each having a first power electrode on a first main surface and a second power electrode on a second main surface; mounting a respective semiconductor die onto the die pad of a respective component position of the leadframe such that the first power electrode is attached to the die pad; mounting a clip onto the dies such that the clip is attached to a respective second power electrode; embedding at least the side faces of the dies and inner surfaces of the leadframe and clip in a mold compound to form a subassembly; and cutting through the clip and leadframe at positions between neighbouring component positions.


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