The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Aug. 10, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shahaji B. More, Hsinchu, TW;

Chandrashekhar Prakash Savant, Hsinchu, TW;

Chun Hsiung Tsai, Xinpu Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H01L 21/285 (2006.01); H01L 21/3215 (2006.01); H01L 21/764 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/28518 (2013.01); H01L 21/3215 (2013.01); H01L 21/764 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/021 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/62 (2025.01); H10D 64/667 (2025.01);
Abstract

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.


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