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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12518833 B1

PDFFull Text
Date of Patent:
Jan. 06, 2026

Filed:

Sep. 22, 2023

Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory

Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Sagar Upadhyay, Folsom, CA (US);

Aliasgar S. Madraswala, Folsom, CA (US);

Bhavya Lokasani, Birmingham, AL (US);

Pratyush Chandrapati, Folsom, CA (US);

Tarek Ahmed Ameen Beshari, San Jose, CA (US);

Assignee:

INTEL NDTM US LLC, Santa Clara, CA (US);

Attorney:

Morgan, Lewis & Bockius LLP

Primary Examiner:

Amir Zarabian

Assistant Examiner:

Justin Bryce Heisterkamp

Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/229 (2013.01);
Abstract

NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.

Find Patent Forward Citations

Upadhyay, Sagar. (2026). Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory (U.S. Patent No. 12518833). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12518833

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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