The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2026
Filed:
Jul. 16, 2021
Micron Technology, Inc., Boise, ID (US);
John D. Hopkins, Meridian, ID (US);
Jordan D. Greenlee, Boise, ID (US);
Alyssa N. Scarbrough, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.