The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Nov. 07, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chia-Ling Chan, New Taipei, TW;

Derek Chen, Taipei, TW;

Liang-Yin Chen, Hsinchu, TW;

Chien-I Kuo, Chiayi County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/00 (2025.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 62/834 (2025.01);
U.S. Cl.
CPC ...
H10D 62/021 (2025.01); H01L 21/02532 (2013.01); H01L 21/0257 (2013.01); H01L 21/0262 (2013.01); H01L 21/2252 (2013.01); H01L 21/324 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 62/834 (2025.01);
Abstract

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.


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