The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Perng-Fei Yuh, Walnut Creek, CA (US);

Chansyun David Yang, Hsinchu, TW;

Keh-Jeng Chang, Hsinchu, TW;

Chan-Lon Yang, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 61/00 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 88/00 (2025.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10B 61/22 (2023.02); H01L 21/0259 (2013.01); H01L 21/76898 (2013.01); H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H10D 64/254 (2025.01); H10D 64/256 (2025.01); H10D 88/101 (2025.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02);
Abstract

A method for fabricating an integrated circuit device is provided. The method includes forming a transistor device over a front side of the semiconductor substrate; forming a first contact feature in the semiconductor substrate, wherein the first contact feature is connected with a back side of a first source/drain feature of the transistor device; and forming a memory structure over a back side of the first contact feature facing away from the first source/drain feature.


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