The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Sep. 08, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Hai Li, Portland, OR (US);
Dmitri Evgenievich Nikonov, Beaverton, OR (US);
Chia-Ching Lin, Portland, OR (US);
Tanay A Gosavi, Portland, OR (US);
Ian Alexander Young, Olympia, WA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 61/00 (2023.01); H01L 25/10 (2006.01); H10N 50/85 (2023.01); H10N 52/00 (2023.01); H03K 19/18 (2006.01); H03K 19/185 (2006.01);
U.S. Cl.
CPC ...
H10B 61/00 (2023.02); H01L 25/105 (2013.01); H10N 50/85 (2023.02); H10N 52/101 (2023.02); H03K 19/18 (2013.01); H03K 19/185 (2013.01);
Abstract
A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.