The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Aug. 23, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Guangsu Shao, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Weiping Bai, Hefei, CN;

Yunsong Qiu, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/33 (2023.02); H10B 12/036 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure, relating to the field of semiconductor technology. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, a bit line and a word line; and the substrate includes a semiconductor layer and a spacer. The capacitor structure is arranged on the substrate, and the spacer is positioned between the capacitor structure and at least a part of the semiconductor layer. The transistor structure and the word line are arranged on a side of the capacitor structure distant from the substrate, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word line, and other one of the source and the drain of the transistor structure is electrically connected to the bit line.


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