The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Jun. 15, 2023
Applicant:
Walton Advanced Engineering, Inc., Kaohsiung, TW;
Inventors:
Assignee:
WALTON ADVANCED ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/3107 (2013.01); H01L 23/5389 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/107 (2013.01);
Abstract
A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.