The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jan. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Pin Chiu, Hsinchu, TW;

Liang-Wei Wang, Hsinchu, TW;

Chen-Chiu Huang, Taichung, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/29 (2013.01); H01L 24/27 (2013.01); H01L 2224/29008 (2013.01); H01L 2224/29124 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/29157 (2013.01); H01L 2224/2916 (2013.01); H01L 2224/29184 (2013.01); H01L 2224/29281 (2013.01);
Abstract

Disclosed semiconductor device manufacturing processes improve the flatness of a passivation layer deposited above a redistribution layer (RDL). When a thin passivation layer is deposited above the RDL, its top surface tends to become very uneven due to the large gaps that typically form over the etched portions of the RDL, particularly when the RDL is disposed over an underlying super high density metal-insulator-metal (MIM) capacitor. In order to reduce the incidence of stress concentration areas on the uneven surface, a thicker passivation layer is instead deposited to minimize gap formation therein, and a chemical mechanical planarization (CMP) process is then performed to further smooth the top surface thereof. Reduction of the stress in this manner reduces the incidence of cracking of the underlying MIM, which improves the overall pass rates of semiconductor devices so manufactured.


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