The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Sep. 24, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Andrew Collins, Chandler, AZ (US);
Srinivas V. Pietambaram, Chandler, AZ (US);
Tarek A. Ibrahim, Mesa, AZ (US);
Aleksandar Aleksov, Chandler, AZ (US);
Telesphor Kamgaing, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/15 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H10D 89/10 (2025.01);
Abstract
Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.