Static random access memory (sram) cell with variable toggle threshold voltage and memory circuit including sram cells

Abstract

A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).