The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
May. 30, 2024
Micron Technology, Inc., Boise, ID (US);
Su Wei Lim, Bayan Lepas, MY;
Senthil Murugan Thangaraj, Fremont, CA (US);
Marco Sforzin, Cernusco sul Naviglio, IT;
Daniele Balluchi, Cernusco sul Naviglio, IT;
Massimiliano Patriarca, Milan, IT;
Giorgio Servalli, Fara Gera d'Adda, IT;
Angelo Visconti, Appiano Gentile, IT;
Antonino Capri′, Bergamo, IT;
Garth N. Grubb, Boise, ID (US);
Amitava Majumdar, Boise, ID (US);
Miguel Mares, Meridian, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.