The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Mar. 21, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rishabh Mehandru, Portland, OR (US);

Cory Weber, Hillsboro, OR (US);

Varun Mishra, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Pratik Patel, Portland, OR (US);

Wonil Chung, Hillsboro, OR (US);

Mohammad Hasan, Aloha, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 64/01 (2025.01); H10D 84/834 (2025.01);
Abstract

Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.


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