The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Oct. 17, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Julien Frougier, Albany, NY (US);

Chen Zhang, Guilderland, NY (US);

Min Gyu Sung, Latham, NY (US);

Heng Wu, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 64/01 (2025.01); H01L 21/3065 (2006.01); H01L 23/528 (2006.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6729 (2025.01); H01L 21/76283 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 64/01 (2025.01); H01L 21/3065 (2013.01); H01L 23/5286 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01);
Abstract

A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.


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