The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Aug. 15, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

John F. Kaeding, Boise, ID (US);

Matthew S. S. Thorum, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/05 (2023.02); H10B 12/03 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source/drain regions.


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