The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Dec. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Karumbu Meyyappan, Portland, OR (US);

Jeffory L. Smalley, East Olympia, WA (US);

Gregorio Murtagian, Phoenix, AZ (US);

Srikant Nekkanty, Chandler, AZ (US);

Eric J.M. Moret, Beaverton, OR (US);

Pooya Tadayon, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01R 12/52 (2011.01); H01R 12/58 (2011.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/49827 (2013.01); H01L 23/5385 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01R 12/52 (2013.01); H01R 12/58 (2013.01);
Abstract

An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.


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