The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andy Chih-Hung Wei, Yamhill, OR (US);

Guillaume Bouche, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/308 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/308 (2013.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.


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