The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Sep. 05, 2022
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Chin-Sheng Wang, Taoyuan, TW;

Ra-Min Tain, Hsinchu County, TW;

Wen-Yu Lin, Taichung, TW;

Tse-Wei Wang, Hsinchu, TW;

Jun-Ho Chen, Taoyuan, TW;

Guang-Hwa Ma, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/66 (2006.01); H01Q 1/38 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/66 (2013.01); H01Q 1/38 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2223/6622 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/2027 (2013.01); H01L 2924/3025 (2013.01);
Abstract

An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.


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