The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2025
Filed:
Dec. 02, 2022
Tong Hsing Electronic Industries, Ltd., Taipei, TW;
Dei-Cheng Liu, Taipei, TW;
Chia-Shuai Chang, Hsin-Chu County, TW;
Ming-Yen Pan, Taipei, TW;
Jian-Yu Shih, Taipei, TW;
Jhih-Wei Lai, Taipei, TW;
Shih-Han Wu, Taipei, TW;
TONG HSING ELECTRONIC INDUSTRIES, LTD., Taipei, TW;
Abstract
A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile