The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 29, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Das Sharma, Saratoga, CA (US);

Swadesh Choudhary, Mountain View, CA (US);

Narasimha Lanka, Dublin, CA (US);

Lakshmipriya Seshan, Sunnyvale, CA (US);

Gerald Pasdast, San Jose, CA (US);

Zuoguo Wu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 11/10 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 11/1004 (2013.01); G06F 13/409 (2013.01);
Abstract

Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.


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