The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Oct. 22, 2020
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Qing Luo, Beijing, CN;

Hangbing Lv, Beijing, CN;

Ming Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H10B 99/00 (2023.01); H10D 8/00 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H10B 99/16 (2023.02); H10D 8/00 (2025.01); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/665 (2025.01); H10D 64/689 (2025.01);
Abstract

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.


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