The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jul. 08, 2022
Applicant:

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventor:

Jing-En Luan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/56 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/19 (2013.01); H01L 2224/211 (2013.01); H01L 2224/215 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92143 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06524 (2013.01);
Abstract

Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.


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