The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Nov. 14, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Kisik Choi, Watervliet, NY (US);

Huai Huang, Clifton Park, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/7682 (2013.01); H10D 30/6729 (2025.01); H10D 62/121 (2025.01); H10D 84/0149 (2025.01); H10D 84/83 (2025.01);
Abstract

One or more systems, devices and/or methods of use provided herein relate to an airgap spacer for power via. The semiconductor device can comprise a power bar wired to a backside power rail, wherein the power bar is located between a first gate of a first field effect transistor (FET) and a second gate of a second FET at least a first airgap between the power bar and at least a portion of the first gate of the first FET and a second airgap between the power bar and at least a portion of the second gate of the second FET, wherein the at least the first airgap and the second airgap maintain parasitic capacitance in the semiconductor device below a threshold.


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