The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Apr. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Pin Chiu, Hsinchu, TW;

Liang-Wei Wang, Hsinchu, TW;

Chen-Chiu Huang, Taichung, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H10D 1/692 (2025.01); H01L 2224/02311 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/1205 (2013.01);
Abstract

A method for forming a semiconductor structure includes forming a metal-insulator-metal (MIM) structure between first passivation layers over a substrate. The method also includes forming a via structure through the MIM structure and the first passivation layers. The method also includes planarizing the via structure. The method also includes forming an RDL structure over the via structure. The method also includes forming a second passivation layer over the RDL structure and the first passivation layers.


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