The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jongjin Lee, Clifton Park, NY (US);

Tae Sun Kim, Ballston Spa, NY (US);

Wonhyuk Hong, Clifton Park, NY (US);

Seungchan Yun, Waterford, NY (US);

Kang-Ill Seo, Springfield, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H01L 23/528 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 64/256 (2025.01); H01L 23/5286 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01);
Abstract

Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.


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