The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jul. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Lin-Yu Huang, Hsinchu, TW;

Chun-Hung Liao, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/76819 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 2223/54426 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01);
Abstract

A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.


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