The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Nov. 08, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott E. Smith, Boise, ID (US);

Sujeet Ayyapureddi, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 7/12 (2006.01); G11C 8/10 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01); G11C 29/1201 (2013.01); G11C 2029/1204 (2013.01);
Abstract

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.


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