The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Nov. 29, 2022
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

I-Hsiu Lo, Hsinchu, TW;

Yung-Jen Chen, Hsinchu, TW;

Yu-Lan Lo, Hsinchu, TW;

Shu-Yi Kao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/20 (2020.01); G06F 30/3308 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/20 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/02 (2020.01);
Abstract

A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.


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